Beams Document 3326-v1

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On-chip power distribution for IC designs and its challenges in deep submicron technologies

Document #:
Beams-doc-3326-v1
Document type:
Talk
Submitted by:
Milorad B. Popovic
Updated by:
Milorad B. Popovic
Document Created:
06 Mar 2009, 11:29
Contents Revised:
06 Mar 2009, 11:29
Metadata Revised:
09 Mar 2009, 05:54
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Abstract:
In this talk, we present an overview of the design and challenges of power network distributions on integrated circuits (ICs). We provide a brief perspective on the development of ICs and introduce the problem of power distribution. As processing technologies shrink to deep submicron regime, more transistors are packed on the same area and at the same time leakage currents become non-negligible causing power consumption and management to become an essential problem. Leakage current reduction is achieved by shutting power off to the idle circuits on the chip referred to as power gating. However, implementation of power gating can impose reliability issues on the power network. We describe the implications and electromigration mechanism that can occur due to power gating. We additionally, discuss the signal and power integrity of power networks and their dependencies to decoupling capacitance efficiency and workload’s frequency for multi-cores systems.
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