Hierarchy Input Constant Input Unused Input Floating Input Output Constant Output Unused Output Floating Output Bidir Constant Bidir Unused Bidir Input only Bidir Output only Bidir
inst37|inst2 19 1 0 1 5 1 1 1 0 0 0 0 0
inst37 24 0 0 0 6 0 0 0 0 0 0 0 0
inst40 0 0 0 0 16 0 0 0 0 0 0 0 0
inst39|inst7 38 4 0 4 6 4 4 4 0 0 0 0 0
inst39|inst6 38 4 0 4 6 4 4 4 0 0 0 0 0
inst39|inst5 38 4 0 4 6 4 4 4 0 0 0 0 0
inst39|inst 38 4 0 4 6 4 4 4 0 0 0 0 0
inst39|inst29 20 0 4 0 12 0 0 0 0 0 0 0 0
inst39 112 0 0 0 20 0 0 0 0 0 0 0 0
inst50|inst32|inst32|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst50|inst32|inst32 33 0 0 0 16 0 0 0 0 0 0 0 0
inst50|inst32 33 8 0 8 16 8 8 8 0 0 0 0 0
inst50 29 0 0 0 12 0 0 0 0 0 0 0 0
inst29 3 4 0 4 69 4 4 4 0 0 0 0 0
inst15|SYNC_CONVST 3 0 0 0 1 0 0 0 0 0 0 0 0
inst15 7 1 0 1 35 1 1 1 0 0 0 0 0
inst9|inst15 3 0 0 0 1 0 0 0 0 0 0 0 0
inst9|inst57 55 0 0 0 38 0 0 0 0 0 0 0 0
inst9|inst13 67 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst9|altsyncram_component|auto_generated 11 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst9 11 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_9 20 0 0 0 11 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_8 18 0 0 0 10 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_7 16 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_6 14 0 0 0 8 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_5 12 0 0 0 7 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_4 10 0 0 0 6 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_31 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_30 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_3 8 0 0 0 5 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_29 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_28 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_27 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_26 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_25 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_24 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_23 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_22 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_21 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_20 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_2 6 0 0 0 4 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_19 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_18 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_17 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_16 34 0 0 0 18 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_15 32 0 0 0 17 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_14 30 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_13 28 0 0 0 15 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_12 26 0 0 0 14 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_11 24 0 0 0 13 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_10 22 0 0 0 12 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_1 4 0 0 0 3 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider|add_sub_0 2 0 0 0 2 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider|divider 48 0 0 0 48 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated|divider 48 0 0 0 48 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH|lpm_divide_component|auto_generated 48 0 0 0 48 0 0 0 0 0 0 0 0
inst9|inst|DIVIDE_BY_AVG_LENGTH 48 16 0 16 48 16 16 16 0 0 0 0 0
inst9|inst|ADD_VALUE_TO_SUM 64 16 0 16 32 16 16 16 0 0 0 0 0
inst9|inst|SYNC_ADC 3 0 0 0 1 0 0 0 0 0 0 0 0
inst9|inst|SYNC_RESET 3 0 0 0 1 0 0 0 0 0 0 0 0
inst9|inst 88 16 0 16 97 16 16 16 0 0 0 0 0
inst9|inst53|inst45|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst45 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst44|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst44 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst43|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst43 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst42|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst42 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst31 68 1 0 1 17 1 1 1 0 0 0 0 0
inst9|inst53|inst41|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst41 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst40|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst40 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst39|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst39 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst8|SETUP_ROM|altsyncram_component|auto_generated 12 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst8|SETUP_ROM 12 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst8|SYNC_DONE 3 1 0 1 1 1 1 1 0 0 0 0 0
inst9|inst53|inst8|SYNC_NEXT 3 1 0 1 1 1 1 1 0 0 0 0 0
inst9|inst53|inst8|SYNC_START 3 1 0 1 1 1 1 1 0 0 0 0 0
inst9|inst53|inst8 7 0 0 0 64 0 0 0 0 0 0 0 0
inst9|inst53|inst38|lpm_mux_component|auto_generated 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst38 33 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst53|inst|CH4DIFF 32 0 0 0 17 0 0 0 0 0 0 0 0
inst9|inst53|inst|CH3DIFF 32 0 0 0 17 0 0 0 0 0 0 0 0
inst9|inst53|inst|CH2DIFF 32 0 0 0 17 0 0 0 0 0 0 0 0
inst9|inst53|inst|CH1DIFF 32 0 0 0 17 0 0 0 0 0 0 0 0
inst9|inst53|inst|CH4SUM 36 2 0 2 18 2 2 2 0 0 0 0 0
inst9|inst53|inst|CH3SUM 36 2 0 2 18 2 2 2 0 0 0 0 0
inst9|inst53|inst|CH2SUM 36 2 0 2 18 2 2 2 0 0 0 0 0
inst9|inst53|inst|CH1SUM 36 2 0 2 18 2 2 2 0 0 0 0 0
inst9|inst53|inst|SYNC_FIFO_FULL 3 0 0 0 1 0 0 0 0 0 0 0 0
inst9|inst53|inst|SYNC_ADC 3 0 0 0 1 0 0 0 0 0 0 0 0
inst9|inst53|inst|SYNC_RESET 3 0 0 0 1 0 0 0 0 0 0 0 0
inst9|inst53|inst 138 0 0 0 130 0 0 0 0 0 0 0 0
inst9|inst53 143 0 0 0 82 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated|dpfifo|wr_ptr 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated|dpfifo|FIFOram 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated|dpfifo|fifo_state 5 0 0 0 11 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated|dpfifo 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4|scfifo_component|auto_generated 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_4 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated|dpfifo|wr_ptr 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated|dpfifo|FIFOram 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated|dpfifo|fifo_state 5 0 0 0 11 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated|dpfifo 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3|scfifo_component|auto_generated 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_3 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated|dpfifo|wr_ptr 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated|dpfifo|FIFOram 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated|dpfifo|fifo_state 5 0 0 0 11 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated|dpfifo 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2|scfifo_component|auto_generated 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_2 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated|dpfifo|wr_ptr 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated|dpfifo|rd_ptr_count 4 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated|dpfifo|FIFOram|altsyncram1 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated|dpfifo|FIFOram 38 0 0 0 16 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated|dpfifo|fifo_state|count_usedw 5 0 0 0 9 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated|dpfifo|fifo_state 5 0 0 0 11 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated|dpfifo 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1|scfifo_component|auto_generated 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|FIFO_CHAN_1 20 0 0 0 27 0 0 0 0 0 0 0 0
inst9|inst52|TEST_DAC_OUTPUT_REG 20 1 0 1 16 1 1 1 0 0 0 0 0
inst9|inst52|ALT_INTEG_CONTROL_2_REG 20 1 0 1 16 1 1 1 0 0 0 0 0
inst9|inst52|ALT_INTEG_CONTROL_1_REG 20 1 0 1 16 1 1 1 0 0 0 0 0
inst9|inst52|RECORD_LENGTH_REG 20 1 0 1 16 1 1 1 0 0 0 0 0
inst9|inst52|COMMAND_REG 20 1 0 1 16 1 1 1 0 0 0 0 0
inst9|inst52 202 17 0 17 170 17 17 17 0 0 0 0 0
inst9|inst16|ADDRESS_LATCH 24 2 0 2 20 2 2 2 0 0 0 0 0
inst9|inst16 60 3 1 3 45 3 3 3 0 0 0 0 0
inst9 206 0 0 0 128 0 0 0 0 0 0 0 0
inst36|SYNC_V1 3 0 0 0 1 0 0 0 0 0 0 0 0
inst36|SYNC_T1 3 0 0 0 1 0 0 0 0 0 0 0 0
inst36 7 0 0 0 4 0 0 0 0 0 0 0 0
inst33|SYNC_RESET 3 0 0 0 1 0 0 0 0 0 0 0 0
inst33 3 0 0 0 15 0 0 0 0 0 0 0 0
inst5|SYNC_CONVST 3 0 0 0 1 0 0 0 0 0 0 0 0
inst5 7 2 0 2 35 2 2 2 0 0 0 0 0