========================================================================== April 19, 2017 Update This new version for the field was made after we discovered why the parameters were getting locked up. It turned out that the Run mode bus accesses were, for some values of Curve Delay, running into the Update interval where the Update Process expected control of the bus but the Run mode would still have it. We updated the dds constants file to fix the switch between the INJPTS Max/Min/Default and Flag/Setting/Reading addresses with the ones for the CRVDLY. This should not have any effect on the code since these CONSTANTS were never referenced in the vhdl. We also updated the Shared Memory *.mif memory initialization file. The new one has better defaults if the FLASH needs to be re-initialized. The change that fixed the lockup problem was made in "Process_Timer_v4.vhd". A pause of 4 us was added between when the Run Mode ends and the Update Interval begins. Since it is the Rewind_Curves signal that actually stops the Run Mode bus accesses, this signal was added to the Process Timer. Previously Rewind_Curves was identical to Start_Update_Interval. ========================================================================== May 8, 2017 Update The new digital damper electronics tries to maintain a phase lock with the DDS LLRF at all times. It started lossing its phase lock on a random, but regular basis. It was finally discovered that occasionally we would provide a bad frequency value to the DDS's for one, 1 us update right after the beam would go away. Loss of the beam gate would drive the phase error feedback contribution to the frequency curve value to zero, through the phase feedback math functions. It was discovered that the occurance of the loss of beam gate was not synchronized to the update clock, and was wrecking the frequency value calculation for one update when it would go away at a critical time in the calculation. The beam gate was synced to the update clock in Version 170508 and the problem has gone away completely. In Freq_Phase_Control_Block.bdf Frequency_Feedback_v8.vhd -- Version 8: In version 8 the trimmed and gated phase error is -- synchronized to the Update_Pulse before being set into the -- multiplication with the phase error gain and addition to the -- frequency curve value. Previously, the beam gate would go away -- and the gated phase error value sometimes went to zero right in -- the middle of the multiplication and the frequency value would -- get the corrupted result. =========================================================================== June 21, 2017 Update The 170222 code update never made it into the field and the recent modifications were not made to this version. The 170222 code was the fix to the RPOS phase shift not following the RPOS Phase Drive input through the entire cycle. The modifications to get the 170508 field version code to track Phase Drive were added in this update, 170620. Changes include: Process_Timer_v6.vhd -- Versoion 6, June 21, 2017 -- In this version we let the DDS_1us_Update run continuously -- after the module start up. When triggered to run we resync the 1us update and -- the Run_Curves signal goes active. In Freq_Phase_Control_Block.bdf Frequency_Feedback_v9.vhd -- Version 9: In version 9 the Update_Pulse is always applied to -- keep firing the DDS update strobe so that phase adjustments due -- to RPOS phase drive would continue smoothly from cycle to cycle. -- Hence, the previous inputs Initialize and Update_Enable were -- eliminated. Phase_Controller_v6 -- version 6 is modified to have a continuous update pulse to keep the -- phase updates to the DDS continually following the RPOS phase drive. -- Also, the Disable_Paraphase signal disables the Transition Trigger. -- Also, reversed DataA and DataB in the subtraction in PARAPHASE_MINUS_REF_PHASE: -- since the last version. Also to DDS_Controller_v3.bdf We changed the Phase_Data[15..0] to DDS Channel 1 from zero (gnd) to 0xC000 (-90deg). This offsets the Transition base phase offset applied to DDS Channels 2 and 3. This causes DDS Ch1 to be in phase with DDS Ch2 when zero RPOS Phase Drive is applied. We also get the proper response from the RPOS phase shift: RFIN(ch1) Leads RFOUT(ch2) when Phase drive is positive. RFIN(ch1) Lags RFOUT(ch2) when Phase drive is negative. =========================================================================== July 28, 2017 Update VME_Ctrl_7 Register is connected up with its bit 0 acting as the Backup Enable control bit. A new implementation of the "Upper_VME_Ctrl_Regs_v2.vhd" allows an input signal (Backup_Trigger) to clear Bit 0 of VME_Ctrl_7. This bit VME_Ctrl_7[0] (Backup_Enable) is input for the new "dds_update_seq_v2.vhd" which controls when backups are triggered. See below. I have a bit in a VME Control Register that will act as the DDS Backup Enable bit. It is VME_Ctrl_7 [0] at byte offset 0x 01 F11C. If you set bit zero to 1 ( or just write 1 to this control register) it will allow a backup when one is needed. When the backup gets started, it will clear this bit. Hence, you can read this register to see if a backup has occurred. When this bit gets set, the rising edge of this bit will SET the Backup_Enable SR Register. This SR Register is reset when the next backup begins. ============================================================================== August 02,2017 Update (170830) Added more control over the FLASH store process. Brian Schupbach added code to the ACNET Slot0 processor to do an ena_store once a day. ============================================================================== August 30, 2017 Update (170830) Put into the field on Module #3 ============================================================================= September 12, 2017 (170912) Made modifications to the Flash memory function to verify proper operation. ============================================================================= September 13, 2017 (170913) Repaired the ELSIF statement in the file Upper_VME_Ctrl_Regs_v2.vhd that was locking up the control register writes after a Flash Backup (store) operation. This only had an effect when the board was in manual VME control with SW[7] down. ============================================================================= September 18, 2017 DAC channel 1 that is used to output the representation of the Freq. Curve was set up to be unipolar with the jumper, where the other channels were bipolar. I changed this to bipolar to match the others. In the dac 1 data scaling I inverted bit 15 and I set the offset and scaling of the 32 bit to 16 bit conversion of the Freq. Word to match that setup on dac channel 3. =============================================================================== September 26, 2017 Enabled the phase offset curves and loaded null phase curves into memory. The Disable Phase Offsets signal into the Freq_Phase_Control_Block has, up until now, been pulled up (Active). It is now connected to VME_Ctrl_3[1] at address offset X"01F10C". This register normally comes up as LOW allowing the Phase Offset Curves to be applied. =============================================================================== September 28, 2017 Established a new field version with DDS_LOWER.sof -- 9/19/2017 DDS_UPPER.sof -- 9/28/2017 UPPER-LOWER.pof -- 9/28/2017 9:22 AM Checksum = 14969CE3 =============================================================================== October 10, 2017 New version of the Phase_Controller_v7 version 7 is modified to fix a problem with the paraphase enabled mode. Originally (July 2016) RF A phase was computed with Ref phase MINUS then Paraphase Sum. At some point to fix the RPOS, this got reversed by doing Paraphase Sum MINUS the Ref phase. This version 7 puts the computation back to Ref phase MINUS Paraphase Sum. This will be the new field version with DDS_LOWER.sof -- 9/19/2017 DDS_UPPER.sof -- 10/11/2017 UPPER-LOWER.pof -- 10/11/2017 9:04 AM Checksum = 14B1D3D3