Joint PSP/Taskforce minutes for 12 Mar 2020 ============================ https://beamdocs.fnal.gov/AD-public/DocDB/ShowDocument?docid=8118 (a) Updates: (1) Penning source: Consulating with RAL about how to start Penning source. Req is in process for new postdoc. (2) Klystron testing: 4 spares tested good, 1 bad, 1 may be bad -- perhaps needs more conditioning. 2 more left to test. (3) Flat injection: DC ramp studies on 11 March. (4) 2nd harmonic: RF measurements completed. Cracked shells sent for cleaning. (5) Wide bore cavities: Low power measurements completed. PA connected. Waiting for high power test. Unfortunately, high bias does not get cavity to extraction frequency. John will modify bias supply to increase bias. (6) Garnet loss improvements: Solenoid design is basically complete. More design required for the test fixture. (7) Mode 2 dampers: Mode 2 measurements were done. RF#7 is being used as the damping cavity. (8) Paraphase controller: Very close to being done. Problem found is bunch rotation. This has been fixed but needs to be tried with beam again. (9) LLRF: see today's demo (b) PIPII updates: (1) Lattice studies: Studies done on 11 March. Orbit tuning to see whether lifetime improves during the week. (2) Magnet girder tests: Girder has been moved to IB2 for sandblasting. Then to E4R. Magnet mover discussion has started. Money for R&D allocated for FY21 and FY22. (3) 20 Hz infrastructure tests: Meeting soon. (4) 50 kV cavity tests: 11, 12, 13, 14 running at 50 kV gap voltage. But 11 failed because of water leak in tuner. (5) BTL to L11 changes: Collimating halo to be simulated. (c) Ed gave an update and demo of the new digital LLRF system (1) The new LLRF system will be able (i) to operate at 20 Hz. (ii) injection time increased from 40 us to 600 us. (iii) RF frequency changed from 38 - 53 MHz to 45 - 53 MHz. (2) The new system is a digitized copy of the analog system. However, there are many improvements: (i) Reduce delay through the system (ii) simplify the architecture from 3 FPGAs to 1 (iii) simplify hardware layout (iv) simplify integration to PIPII control system (v) increase digital and RF diagnostics (vi) ability to run at 20 Hz (vii) ability to simplify future control config upgrades (viii) simplify future FPGA upgrades (3) A "fake" beam response was made with a 2nd order low pass filter. It was tuned to look like the measured beam response. (4) The hardware prototype consists of (i) Altera CYCLONE 5 (ii) 16*14 bit ADCs (iii) 8* 14 bit DACs (5) The protoype controller has shown in improvement over the current system by reducing the delay by 1.7 us from 4.5 us to 2.8 us.